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1 ? fn9158.1 ISL6172 dual low voltage hot swap controller this ic targets dual voltage hot swap applications across the +2.5v to +3.3v bias supply voltage range with a second lower voltage rail down to less than 1v. it features a charge pump for driving external n-channel mosfets, regulated current protection and duration, outp ut undervoltage monitoring and reporting, optional latch-off or retry response, and adjustable soft-start. the current regulation level (cr) for each rail is set by two external resistors and each cr duration is set by an external capacitor on the tim pin. after the cr duration has expired the ic then quickly pulls down the associated gate(s) output turning off its external fet(s). the ISL6172 offers a latched output or indefinite auto retry mode of operation. pinout 28 lead qfn top view features ? dual supply hot swap power distribution control to <1v ? less than 1s response time to dead short ? overcurrent circuit breaker fault isolation and programmable current regulation level protection functions ? programmable current regulation duration ? charge pump allows the use of n-channel mosfets ? rail independent control, monitoring and reporting i/o ? adjustable ramp up for inrush protection during turn on ? two levels of overcurrent detection provide fast response to varying fault conditions ? latch-off or auto reset response to fault functions ? adjustable current regulation threshold as low as 20mv ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free applications ? power supply sequencing, distribution and control ? hot swap/electronic breaker circuits ? network hubs, routers, switches ? hot swap bays, cards and modules ordering information part number temp. range (c) package pkg. dwg. # ISL6172drza * 0 to +85 28 ld 5x5 qfn (pb-free) l28.5x5 ISL6172drza-t * 0 to +85 28 ld 5x5 qfn (pb-free) l28.5x5 ISL6172eval3 evaluation platform * intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-f ree products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 rtr /ltch gnd pgnd cpq- bias cpq+ cpvdd vs1 uv1 en1 ocref en2 uv2 vs2 sns2 vo2 ss2 gt2 flt2 pg2 ct2 sns2 vo1 ss1 gt1 flt1 pg1 ct1 v1(in) v2(in) v1(out) v2(out) rsns1 rsns2 rset1 rset2 figure 1. typical application ISL6172 en1 en2 rtr /ltch bias cpq+ cpq- cpvdd pgnd gnd ct1 ct2 vs2 sns2 gt2 vo2 uv2 pg2 flt2 flt1 pg1 ss1 ss2 ocref gt1 vo1 uv1 vs1 sns1 data sheet june 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 block diagram q rsns 3k 10k 10k x2 charge pump x2 charge pump rset current mirror por and bandgap 633mv 1.178v 10v(out) 1.178v 4 iref iref 633mv 1.178v load flt1 pg1 ct1 ss1 uv1 ocref en1 rtr/ltch cpq+ cpq- cpvdd bias vs1 sns1 gt1 vo1 pgnd gnd bias bias 10v cpvdd cpvdd oc timer & logic soft start amplifier current limit amplifier with ?quick-slew? 20ua 10ua 10ua woc comparator oc comparator + + + + - - - - + + - - timeout comparator uv comparator io iset ISL6172 vin vo rref cp cv css rs1 rs2 ct 30ua figure 2. ISL6172 - internal block-diagram of one channel ISL6172
3 pinout 28 lead qfn top view 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 rtr /ltch gnd pgnd cpq- bias cpq+ cpvdd vs1 uv1 en1 ocref en2 uv2 vs2 sns2 vo2 ss2 gt2 flt2 pg2 ct2 sns2 vo1 ss1 gt1 flt1 pg1 ct1 pin descriptions pin name function description 1 sns1 current sense input this pin is c onnected to the current sense resistor and control mosfet drain node. it provides current sense signal to the internal comparat or and amplifier in conjunction with vs1 pin. 2 vo1 output voltage 1 this pin is connected to the control mosfet switch source, which connects to a load. internally, this voltage is used for oc comparator input and for ss control. 3 ss1 soft-start duration set input a capacitor from this pin to ground sets the output soft-start ramp slope. this capacitor is charged by the internal 10a current source setting the soft -start ramp. the output voltage ramp tracks the ss ramp by controlled enhancement of fet gate. once ramp-up is completed, the capacitor is discharged. if common capacitor is used (by tying ss1, ss2 together and the capacitor to gnd from the connection) then both the outputs track each other as they ramp up. 4 gt1 gate drive output direct connection to the gate of the exter nal n-channel mosfet. at turn-on the gate will charge to vin1+5.3v with a 20a source. 5flt1 fault output this is an open drain output. it asserts (pul ls low) once the current regulation duration (determined by the ctx timeout cap) has expired. 6pg1 power good output this is an active low, open drain output. w hen asserted (logic zero), it indicates that the voltage on uv1 pin is more than 643mv (633mv + 10mv hysteresis). this output is valid at vbias >1v. 7 ct1 timer capacitor a capacitor from this pin to ground contro ls the current regulation duration from the onset of current regulation to channel shutdown (current limit ti me-out). once the voltage on ctx cap reaches v ct_vth the gate outputs are pulled down and the flt(s) is asserted. the duration of current limit time-out = (c tim *1.178)/10a when the oc comparator trips and the rtr /ltch pin is left floating (or pulled high), the ic?s faulty channel remains shut down for 64 cy cles (each cycle length is equal to the current limit time-out duration). 8rtr / ltch retry or latch input this input dictates the ic behavior (for either channel) under oc condition. if it is pulled high (or left floating), the ic will shut down upon oc detection. if it is pulled low, the ic will go into retry mode after an interval determined by the capacitor on ctx pin. the faulting channel will remain shut down for 64 cycles and will try to come out of it on 65th cycle. each cycle l ength is determined by the formula shown in ct pin description. 9 gnd chip gnd this pin is also internally shorted to the metal tab at the bottom of the ic. ISL6172
4 10 pgnd charge pump ground. both gnd and pgnd must be tied together. 11 cpq- charge pump capacitor low side flying cap lowside 12 bias chip bias voltage provides ic bias. should be 2v to 4v for ic to function normally. this pin can be powered from a supply voltage that is not being controlled. it is preferable to use 3.3v even if the channels being controlled are 2.5v or lower because more gate drive voltage will be available to the mosfets. 13 cpq+ charge pump capacitor high side flying cap highside. use of 0.1f for 2.5v bias and 0.022f for 3.3v bias is recommended. 14 cpvdd charge pump output this is the voltage used for some internal pullups and bias. use of 0.47f (minimum) is recommended. 15 ct2 timer capacitor same function as pin 7 16 pg2 power good output same function as pin 6 17 flt2 fault output same as pin 5 18 gt2 gate drive output same as pin 4 19 ss2 soft-start duration set input same as pin 3 20 vo2 output voltage 2 same as pin 2 21 sns2 current sense input same as pin 1 22 vs2 current sense reference voltage input for one of the two voltages. provides a 20a current source for the iset series resistor which sets the voltage to which the sense resistor ir drop is compared. 23 uv2 undervoltage monitor input this pin is one of the two inputs to the undervoltage comparator. the other input is the 633mv reference. it is meant to sense the output volt age through a resistor divider. if the output voltage drops so that the voltage on the uv pin goes below 633mv, pg2 is deasserted. 24 en2 enable this is an active low input. when asserted ( pulled low), the ss and gate drive are released and the output voltage gets enabled. when deasserted (pull ed high or left floating), the reverse happens. 25 ocref ref. current adj. allows adjustment of the reference current through r set and the internal current regulation set resistor, thus setting the thresholds for cr, oc and woc. 26 en1 enable input same as pin 24 27 uv1 undervoltage monitor input same as pin 23 28 vs1 current sense reference same as pin 22 pin descriptions (continued) pin name function description ISL6172
5 absolute maximum rati ngs thermal information vbias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5v gtx, cpq+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +12v enx , rtr /ltch, snsx, pgx , fltx, vsx, ctx, uvx, ssx, cpq-, cpvdd. . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5vdc output current . . . . . . . . . . . . . . . . . . . . . . . short circuit protected esd rating human body model (per mil-std-883 method 3015.7) . . . . .1kv machine model (per eiaj ed-4701 method c-111) . . . . . . . . .75v charged device model (per eos/esd ds5.3, 4/14/93) . . . 1.5kv operating conditions vbias/vin1 supply voltage range. . . . . . . . . . . . +2.25v to +3.63v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0c to 85c thermal resistance (typical, notes 1, 4) ja (c/w) jc (c/w) 5x5 qfn package . . . . . . . . . . . . . . . . 42 12.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c for recommended soldering conditions, see tech brief tb389. (qfn - leads only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. all voltages are relative to gnd, unless otherwise specified. 3. 1v (min) on the bias pin required for flt to be valid. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = 2.5v to +3.3v, t a = t j = 0c - 85c, unless otherwise specified. parameter symbol test conditions min typ max unit current regulation control current regulation threshold voltage v crvth_1 riset = 1.25k 1%, i set = 20a202530mv current regulation accuracy v crvth_1 r riset = 1.25k 1%, i set = 20a -20 +20 % current regulation threshold voltage v crvth_2 riset = 2.50k 1%, i set = 20a455055mv current regulation accuracy v crvth_2 r riset = 2.50k 1%, i set = 20a -10 +10 % ct threshold voltage v ct_vth 1.156 1.178 1.200 v ct charging current i ct 10 a gate drive gate response time from woc (open) pd_woc_open gate open 100mv of overdrive on the woc comparator 3ns gate response time from woc (loaded) pd_woc_load gate = 1nf 80 ns gate response time in current regulation mode (loaded) pd_cr_load gate = 1nf 120% load current 4ms gate response time in ?quick-slew? pull- down mode (loaded) pd_oc_load gate = 1nf 22mv of overdrive on amplifier input 50 s gate turn-on current igate gate = 2v vv s = 2v v sns = 2.1v 14 18.5 22 a current limit amplifier transconductance gm vv s - v sns 1 = -25mv 0.35 ms gate pull down resistor (woc, fault or off conditions) ig_woc t j = 25c gate = 2v 18 25 42 ? gate pull down resistor (?quick-slew? mode) ig_qs t j = 25c gate = 2v 91113k ? ISL6172
6 gate voltage v gate bias = 2.5v (see graph on page 7) 8.8 9.3 9.7 v 2.1 < bias < 2.5 (see graph on page 7) 8v bias supply current i bias v bias = 3.3v 5 10 ma por rising threshold vin_por_l2h 2.1 v por falling threshold vin_por_h2l 2.0 v por threshold hysteresis vin_por_hys 10 mv i/o undervoltage comparator falling threshold v uv_vthf 620 635 650 mv undervoltage comparator hysteresis v uv_hyst 11 16 21 mv en rising threshold pwr_vth_r v bias = 2.5v 1.60 1.95 2.25 v en falling threshold pwr_vth_f v bias = 2.5v 0.97 1.10 1.30 v en hysteresis pwr_hyst v bias = 2.5v 600 850 1100 mv pg pull-down voltage vol_pg i pg = 8ma 0.047 0.4 v flt pull-down voltage (note 3) vol_flt i flt = 8ma 0.047 0.4 v soft-start charging current iq_ss vss = 1v 10 a charge pump cpvdd v_cpvdd v bias = 2.0v 3.6 3.8 4.0 v cpvdd v_cpvdd v bias = 3.3v 4.9 5.2 5.5 v cpvdd v_cpvdd v bias = 3.3v t = 25c external user load = 6ma 5.0 v electrical specifications v dd = 2.5v to +3.3v, t a = t j = 0c - 85c, unless otherwise specified. (continued) parameter symbol test conditions min typ max unit typical performance curves (at 25c unless otherwise specified) figure 3. i_bias vs v_bias figure 4. por rising threshold vs temperature 6 5 4 3 2 1 0 i_bias (ma) 1.0 1.5 1.8 2.3 2.8 3.2 3.7 v_bias (v) cpq = 22nf, cpvdd = 0.1f 2.010 2.005 2.000 1.995 1.990 1.985 1.980 por (v) 0 25406085 temperature (c) ISL6172
7 figure 5. v gate vs v_bias figure 6. por falling threshold vs temperature figure 7. gate drive vs temperature figure 8. pg_vol vs temperature figure 9. woc response vs load capacitance figure 10. response time vs i o *r sns typical performance curves (at 25c unless otherwise specified) (continued) 12 10 8 6 4 2 0 v gate (v) 1.8 2.2 2.8 3.6 4.5 v_bias (v) cpq = 22nf, cpvdd = 0.1f 22.43.24 1.952 1.950 1.948 1.946 1.944 1.942 1.940 por (v) 0 25406085 temperature (c) 19.2 19.0 18.8 18.6 17.8 17.4 gate drive (a) 025406085 temperature (c) 18.4 18.2 17.6 0.25 0.20 0.15 0.10 0.05 0.00 pg_vol (v) 0 25406085 temperature (c) i pg = 8ma 10000 1000 100 10 1 t response (ns) 1 5 10 15 20 c g (nf) 3 0.01 10000 1000 100 10 1 t response (s) 31 40 56 68 84 io*r sns (mv) 35 26 77 44 29 (i set = 20a, r set *i set = 22mv) ISL6172
8 figures 12 and 13 are actual scope shots under different circuit configurations that are possible with this ic. figure 13 shows that the part is capable of limiting the inrush current to the value set by the current regulation amplifier in absence of or very small sized ss caps. figure 13 is for the normal circuit shown on the front page. figure 11. woc pulldown vs temperature figure 12. ss limited start-up - ss cap 0.033f in place figure 13. current limited start-up: ss cap removed, i cr set to 2.2a. note max inrush current remains at i cr set level (2.2a). typical performance curves (at 25c unless otherwise specified) (continued) 24.0 23.5 23.0 22.5 22.0 woc pulldown r ( ? ) 025406085 temperature (c) ch1: v o 2, ch3: i in ISL6172
9 detailed description of operation ISL6172 targets dual voltage hot-swap applications with a bias of 2.1v to 3.6vdc an d the voltages being controlled down to 0.7vdc. the ic?s main function is to limit and regulate the inrush current into the loads. this is achieved by enhancing an external mosfet in a controlled manner. in order to fully enhance the mosfet, the ic must provide adequate gate to source voltage, which is typically 5v or greater. hence, the final steady-state voltage on gate (gt) pin must be 5v above the load voltage. two internal charge- pumps allow this to happen. controlled soft-start the output voltages are monitor ed through the vo pins and slew up at a rate determined by the capacitors on the soft- start (ss) pin, as illustrated in figure 14. 20a of gate charge current is available. t he soft-start amplifier controls the output voltage by robbin g some of the gate charge current thus slowing down the mosfet enhancement. when the load voltage reaches its set level, as sensed by its respective uv pin through an external resistor divider, the power good (pg ) output goes active, signaling that the output voltage has reached its set limit. current monitoring and protection the ic monitors the load current (io) by sensing the voltage- drop across the low value current sense resistor (r sns ), which is connected in series with the mosfet mentioned earlier and shown in the diagram on page 2, through sense (sns) and voltage set (vs) pins. the latter is through a resistor, r set , as shown. three levels of overcurrent detection are available to protect against all possible fault scenarios. these levels are: 1. current limit or current regulation (cr) 2. ?quick slew? mode 3. way overcurrent (woc) each of these modes is described in detail as follows: 1. current limit or current regulation (cr) mode: when the load current reaches the cu rrent regulation threshold, the current amplifier loop closes and the circuit behaves like a current source. the current regu lation threshold is set by setting a reference current, i set , through r set by selecting an appropriate resistor between ocref and gnd, which sets i ref . the relationship between i ref and i set is i ref = 4*i set , where i ref = vocref/rocref = 1.178/rocref. i ref would typically be set at 80a. selecting appropriate values for r set and r sns such that when i o = i cr , the operating mode is shown in figure 15 (please ignore the portion shown in dotted line for now). when the circuit enters this mode, increased voltage drop across the mosfet is sensed by the oc comparator, which sets off the timer. ct begins to charge from an inte rnal 10a current source. the amount of time it takes for this cap to charge to 1.178v sets up the current regulation duration and upon expiration of which the mosfet gate is pulled down by 80ma current sink unless the load current level drops back to a level below the current regulation threshold level prior to that. in that case, the current regulation mode is no longer active, the mosfet is allowed to fully enhance and the ic discharges the c t cap. if rtr /ltch pin is left open or pulled to bias, the output remains latched off after the expiration of the time-out period determined by c t . if rtr /ltch pin is pulled to gnd, the ic automatically retries to turn on the mosfet after a wait period, during which c t is charged and discharged 64 times and the retry attempt takes plac e on the 65th time. this wait period allows the mosfet junction to cool down. q ss1 g t 1 v o 1 10v cpvdd soft- start amplifier 20a 10a + 30a vo 0 0 vin cpvdd vin + - - figure 14. soft-start operation (eq. 1) io*r sns = i set *r set q rsns 3k rset 4 iref vs1 sns1 gt1 10v current limit amplifier (ota) 20a + - iset vin vo + - + - ISL6172 current regulation iset*rset = io*rsns 10k vqs =1.2*iset*rset vqs + - ?quick slew? figure 15. current regulation and quick-slew operation mode: ISL6172
10 2. ?quick slew? mode: this mode comes in to effect when the di/dt of the load is too fast for the current regulation to see and is 20% or more above the current regulation limit. it shares the same circuit block as the current regulation amplifier in the block diagram. the purpose of having this mode is to ensure the current does not go too high for too long. while in this mode, the gate of the mosfet is allowed to be pulled down passively with an internal resistor of approximately 10k. once the current level reaches the current regulation set level, th e current regulation amplifier takes over. 3. way overcurrent (woc) mode: this mode is designed to handle hard shorts on the load side, which can result in very high di/dt. typically, the curr ent limit set for this mode is 300% of the current regulation li mit. this mode uses a very fast comparator, which directly looks at the voltage drop across r sns and pulls the gate very quickly to gnd (as shown in figure 16) and immedi ately releases it. if the woc is still present, the ic enters current regulation mode and the rest of the current regulation behavior follows as described earlier under current regulation mode. additionally, as shown in the block diagram, there is also an ?oc comparator?, which looks at the combined mosfet and rsense voltage drop. when the mosfet drop exceeds the r sns drop by 60mv, timeout circuit starts ticking and ctx is allowed to charge. if t he 60mv drop remains in effect until after the time-out period expires (ctx voltage exceeding 1.178v), the gate of the mosfet is pulled down, ssx capacitor is discharged, flt is asserted and a new ss sequence is allowed to begin after enx recycle or by keeping the rtr /ltch pin pulled low. the voltage on ocref pin is the same as the internal band- gap reference voltage, which is 1.178v (nominal). a resistor to gnd from this pin sets the reference current (and hence reference voltage) for the current limit amplifier and oc/woc comparators. the current regulation (cr) duration is set by the capacitor on ct pin to gnd. once the voltage on this pin reaches 1.178v, the cr duration expires. fault (flt ) pin goes active (pulls low), signaling the load of a fault condition and the gate (gt) pin gets pulled low. retry vs latched fault operational modes: rtr /ltch pin dictates the ic behavior after the gate (gt) pin pulls down following a current regulation or oc or woc condition. if the rtr /ltch pin is left floating, the gate pin will remain latched off. it can only be released by de- asserting and reasserting the enable (en ) input. if rtr /ltch pin is pulled to gnd, then the retry mode will be activated. in this mode the ic will automatically attempt to turn-on the mosfet after a delay, determined by the capacitor on ct pin. in the retry mode, the internal logic charges and discharges the ct cap 64 times during ?wait? period. on the 65th time, retry takes place. if the fault is cleared, the normal power up will continue and fault will clear. if not, the ic will c ontinue to retry indefinitely. bias and charge pump voltages: the bias pin feeds the chip bias voltage directly to the first of the two internal charge pumps, which are cascaded. the output of the first charge pump, in addition to feeding the second charge pump, is accessible on cpvdd pin. the voltage on cpvdd pin is approximately 5v. it also provides power to the por and band-gap circuitry as shown in the block diagram. a capacitor connected externally across cpq+ and cpq- pins of the ic is the ?flying? cap for the charge-pump. the second charge-pump is used exclusively to drive the gates of the mosfets through the 20a current sources, one for each channel. the output of this charge pump is approximately 10v as shown in the block diagram. q rsns 3k rset vs1 sns1 gt1 - + io iset vin vo + - + - ISL6172 25 ? woc comparator gate pulldown current figure 16. woc operation ISL6172
11 tracking the two channels can be forced to track each other by simply tying their ss pins together and using a common ss capacitor. in addition, their en pins also must be tied together. typical start-up waveforms in this mode are shown in figure 17 above. if one channel goes down for any reason, the other one will too. one important thing to note here is that only the overcu rrent latch-off mode will work. autoretry feature will not work. retry must be controlled manually through en . typical hot-plug power up sequence 1. when power is applied to the ic on bias pin, the first charge pump immediately powers up. 2. if the bias voltage is 2.1v or higher the ic comes out of por. both ss and ct caps remain discharged and the gate (gt) voltage remains low. 3. enx pin, when pulled low (below it?s specified threshold), enables the respective channel. 4. ssx cap begins to charge up through the internal 10a current source, the gate (gt) voltage begins to rise and the corresponding output voltage begins to rise at the same rate as the ss cap voltage. this is tightly controlled by the soft-start amplifier shown in the block diagram. 5. ctx cap begins to charge at the same time as the corresponding ss cap. 6. fault (flt ) remains deasserted (stays high) and the output voltage continues to rise 7. if the output voltage reaches its full value before the corresponding ctx cap voltage reaches 1.178v, the latter gets discharged and the flt remains deasserted. else, the channel shuts down and flt is asserted. 8. if the voltage on uv pin exceeds 633mv threshold as a result of rising vo, power good (pg ) output goes active. 9. at the end of the ss interval, the ss cap voltage reaches cpvdd and remains charged as long as en remains asserted or ct timer is not timed out. the latter indicates expiration of current regulation duration. state diagram this is shown in figure 18. it provides a quick overview of the ic operation and can also be used as a troubleshooting road map. ch1: v o 1, ch2: v o 2, t = 2ms/div, c ss = 0.066f figure 17. tracking mode waveforms ISL6172
12 ic operation state diagram soft start (tss) reset & latch off state flt asserted state quick slew/cr state run oc timer state valid output voltage available pg asserted gate pulldown no power pg & flt outputs valid flt cleared apply power bias>1v bias>2v en asserted en de-asserted rtr/ltch = l t ss> t ct rtr/ltch = h t *>tc t io>i cr oc comp trip (woc) io>i cr io>>i cr io>i cr and i o< woc count 64 pulses & reset vuv>645mv t *(vin-100mv) and vout<(vin-100mv) and * ?t? is either equal to tss or the time for which the current remains at i cr or greater level, whichever is applicable figure 18. ISL6172
13 applications information selection of exte rnal components typical application circuit of figure 2 has been used for this section, which provides guidelines to select the external component values. mosfet (q1) this component should be selected on the basis of its r ds(on) specification at the expe cted vgs (gate to source voltage). one needs to ensure that the combined voltage drop across the rsense and r ds(on) at the desired maximum current (including transients) will still keep the output voltage above the minimum required level. power dissipation in the device under short circuit condition should also be an important consideration especially in auto-retry mode (rtr /ltch pin pulled low). using ISL6172 in latched off mode results in lower power dissipation in the mosfet. current sense resistor (r sns ) the voltage drop across this resistor, which represents the load current (io), is compared against the set threshold of the current regulation amplifier. the value of this resistor is determined by how much combined voltage drop is tolerable between the source and the load. it is recommended that at least 20mv drop be allowed across this resistor at max load current. this resistor is expec ted to carry maximum full load current indefinitely. hence, the power rating of this resistor must be greater than i o(max) 2 *r sns . current set resistor (r set) this resistor directly sets the threshold fo r the current regulation amplifier and indirectly sets the same for the oc and woc comparators in conjunction with r sns . once r sns has been selected, use equation 1 to calculate r set . use 20a for i set in a typical application. reference current set resistor (r ref ) this resistor sets up the current in the internal current source, i ref /4, shown in figure 2 for the comparators. the voltage at the ocref pin is the same as the internal bandgap reference. the current (i ref ) flowing through this resistor is simply: i ref = 1.178/r ref this current, i ref , should be set at 80a to force 20a in the internal current source as show n in figure 2, because of the 4:1 current mirror. selection of rs1 and rs2 these resistors should be selected based on where the user wants to set the uv detect point. the uv comparator detects the undervoltage condition when it sees the voltage at uv pin drop below 0.633v. the resistor divider values should be selected accordingly. charge pump capa citor selection (c p and c v ) c p is the ?flying cap? and c v is the smoothing cap of the charge pump, which operates at 450khz set internally. the output resistance of the charge pump, which affects the regulation, is dependent on c p value and its esr, charge- pump switch resistance, frequency and esr of the smoothing cap, c v . the output resistance can be approximately calculated us ing the following equation: r out = r int + 4*esr c p +esr c v + [1/(f*c p )] where, r out = output resistance r int = combined internal resistance (25 ? ) esr c p = esr of c p esr c v = esr of c v f = 450khz it is recommended that c p be kept within 0.022f (minimum) to 0.1f (maximum) ra nge. only cera mic cap is recommended. use 0.1f cap if cpvdd output is expected to power an external circuit, in which case the current draw from cpvdd must be kept below 10ma. c v should at least be 0.47f (ceramic only). higher values may be used if low ripple performance is desired. time-out capacitor selection (c t ) this capacitor controls the ti me-out period. as shown in figure 2, when the voltage across this capacitor exceeds 1.178v, the time-out comparator detects it and pulls down the gate voltage thus shutting down the channel. an internal 10a current source charges this capacitor. hence, the value of this capacitor is determined by the following equation: c t = (10a * t out )/1.178 where, t out = desired time-out period. important note: selection of c t and c ss should be such that the soft-start period is always shorter than the time-out period. otherwise the output will remain shut down. soft-start capacitor selection (c ss ) the rate of change of voltage (dv/dt) on this cap, which is determined by the internal 10a current source, is the same as that on the output cap. henc e, the value of this capacitor directly controls the inrush current amplitude during hot swap operation. c ss = c o *(10a/i inrush ) where, c o = load capacitance i inrush = desired inrush current ISL6172
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com i inrush is the sum of the dc steady-state load current and the load capacitance charging cu rrent. if the dc steady-state load remains disabled until after the soft-start period expires (pgx could be used as a load enable signal, for example), then only the capacitor charging current should be used as i inrush . ISL6172 evaluation platform the ISL6172eval3 is the primary evaluation board for this family. the board is a standalone evaluation platform and it only needs input bias and test voltages. the evaluation board has been designed with a typical application and accessibility to all the features in mind to enable a user to understand and verify these features of the ic. the circuit is designed for 2a for each input rail but it can easily be scaled up or down by adjusting some component values. led indicators are provided to indicate fault and/or power good status. the switches are there to perform enable function for each channel and to select autoretry or latchoff mode. there are two input voltages, one for each channel plus there is optional ?+5v? input. the latter is to test the pull-up capability of flt and pg outputs to +5v. the loop jumpers are there to facilitate curr ent measurement using an oscilloscope current probe. pins ss1 and ss2 of the ic are available on header j2 as test points so that they can be tied together to achieve tracking between vo1 and vo2. each channel is preloaded with capacitive and resistive loads. extra load can be externally applied if necessary. the outputs are brought out to banana sockets to allow external loading if desired. ISL6172
15 ISL6172 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l28.5x5 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-1 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n282 nd 7 3 ne 8 7 3 p- -0.609 --129 rev. 0 02/03 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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